1. Field of the Invention
The present invention is related to very large scale integrated circuit logic designs and more particularly to timing analysis tools for gate array logic designs.
2. Background Description
State of the art integrated circuit (IC) logic chips have logic that is interactively placed and wired, principally, based upon logic timing. Generally, for a typical synchronous logic chip, logic paths are bracketed by flip flops or registers that are clocked by on-chip clocks, i.e., a clock sets a flip flop at the beginning of a path and after a given (clock) period, the results are locked in a second flip flop at the other end of the path. So, the time between clock edges determines how much time is available for a signal to propagate along the particular path.
Any extra time between the calculated propagation delay time and the clock period is known as slack. Normally by design, there is a required minimum amount of slack specified. Any path having less than that specified required amount of slack is identified as what is known as a critical path, i.e., a path that is most sensitive and so most likely to encounter timing related problems.
A graph may be generated for a logic chip that indicates slack in individual paths and is known as a slack graph. The slack graph may be used to determine which path and associated nets on the chip are critical. Thus, a slack graph may be used to facilitate logic block placement. Further, once critical paths are identified, the slack graph may be used to guide block relocation and path re-design in order to adjust placement of identified critical nets. Building a slack graph and using it as a guide for adjusting logic placement is well known in the art.
A typical logic placement tool can trade off between net length and block placement. By identifying timing critical nets, the tool can adjust either to achieve a better timing. Normally, after identifying critical paths, only those critical path nets are considered for optimization to eliminate criticalities, e.g., re-locating cells, repowering cells and in severe cases, redesigning logic for the critical path. This is a long arduous task. Further, redesigning one net in the critical path is not considered with respect to its affect on other nets in other critical paths that might also include the redesigned critical net. Consequently, redesigning one net in one critical path might help or hinder fixing other critical paths.
Thus, there is a need for a simple critical path analysis tool.
The present invention is a method of integrated circuit design and circuit design tool. Critical paths are identified in an integrated circuit design. Identified edges are weighted. Edges are assigned a higher weight, responsive to the number of critical paths in which they are included. A net criticality is assigned to each weighted edge based upon the edge""s weight. Cells are re-placed and wired according to net criticality.